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Reset and Reset Configuration
Table 5-2. E 2 PROM Hard Reset Configuration Word
Field
ERB
EXMC
Data
Bus
Bits
0
1
Prog
Value
[Bin]
’0’
’0’
Implication
Internal Arbitration Selected.
Internal Memory Controller. CS0 active at
Offset In
Flash
[Hex]
0
Value
[Hex]
04
system boot.
CDIS
EBM
BPS
CIP
2
3
4:5
6
’0’
’0’
‘01’
’0’
Core Enabled.
‘0’ - Single PowerQUICC II Mode
8 Bit Boot Port Size
Sets Core Initial Prefix MSR[IP]=1, so that
system exception table is placed at address
0xFFF00100 regardless of FLASH memory
size
ISPS
7
‘0’
64 bit internal space for external master
accesses. In fact don’t care on this board since
external master is not supported.
L2CPC
8:9
‘01’
CI/BADDR(29)/IRQ2 selected as IRQ2
8
72
WT/BADDR(30)/IRQ3 selected as IRQ3
L2_HIT/IRQ4 selected as IRQ4
CPU_BG/BADDR(31)/IRQ5 as IRQ5)
DPPC
10:11
‘11’
Data Parity Pin configuration as:
DP0 as EXT_BR2
DP1 as EXT_BG2
DP2 as EXT_DBG2
DP3 as EXT_BR3
DP4 as EXT_BG3
DP5 as EXT_DBG3
DP6 as IRQ6
DP7 as IRQ7
Reserved
ISB
12
13:15
’0’
’010’
Reserved.
IMMR initial value 0x0F000000, i.e., the
internal space resides initially at this address.
BMS
BBD
16
17
’0’
’0’
Boot memory (E 2 PROM) at 0xFE000000.
ABB/IRQ2 pin is ABB
10
36
DBB/IRQ3 pin is DBB
MMR
LBPC
APPC
18:19
20:21
22:23
’11’
’01’
’10’
Mask Masters Requests. Boot Master is 60x.
Local Bus pins function as PCI bus.
MODCK1/AP(1)/TC(0) functions as BKSEL0
MODCK2/AP(2)/TC(1) functions as BKSEL1
MODCK3/AP(3)/TC(2) functions as BKSEL2
IRQ7~/APE~ functions as IRQ7~
CS11~/AP(0) functions as CS11~
MPC8272ADS User Guide
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